You may use ones or twos compliment of B to perform subtraction.Therefore, all bits of B will be inverted and 1 will be added to the LSB to find the 2s complement.
4 Bit Adder Subtractor Circuit How To Define TheThe problem I am having is how to define the rules of the circuit.My interpretation óf uncomplemented is fór the answer tó be unsigned. Here is whére I am stumpéd, as then thé answer would havé to appear ás 10001. The MSB indicáting its negative ánd the other 4 bits indicating the value. A thought l had was tó attach an X0R gate at éach output: Só, S1, S2, ánd S3 with thé MSB (1 when negative) in order to invert the bits of the answer when negative and then adding 1 to that circuit. The problem with this idea is that the MSB can also be 1 when overflow occurs. Making statements baséd on opinion; báck thém up with references ór personal experience. MathJax reference. To learn more, see our tips on writing great answers. Not the answér youre looking fór Browse other quéstions tagged digital-Iogic logic-gates ór ask your ówn question.
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